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upi confidential UP9305 1 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual 5v/12v synchronous-rectified buck controller the UP9305 is a compact synchronous-rectified buck controller specifically designed to operate from 5v or 12v supply voltage and to deliver high quality output voltage as low as 0.6v for UP9305s/ w (linear ocp). the UP9305 adopts constant frequency, voltage mode control scheme, featuring easy-to-use, low external component count, and fast transient response. fixed 300khz operation provides an optimal level of integration to reduce size and cost of the power supply. this controller integrates internal mosfet drivers that support 12v+12v bootstrapped voltage for high efficiency power conversion. the bootstrap diode is built-in to simplify the circuit design and minimize external part count. other features include internal soft start, over/under voltage protection, over current protection and shutdown function. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part is available in psop-8l package. operates from 5v or 12v supply voltage 3.3v to 12v v in input range v ref with 1.0% accuracy: UP9305s /w : 0.6v v ref UP9305t/q: 0.8v v ref stand alone mode operation simple single-loop control design voltage-mode pwm control fast transient response fixed 300khz switching frequency high-bandwidth error amplifier 0% to 90% duty cycle lossless, adjuatable over current protection uses lower mosfet r ds(on) UP9305s/w: linear ocp UP9305t/q: fixed ocp internal soft start integrated boot diode psop-8l package rohs compliant and halogen free power supplies for microprocessors or subsystempower supplies cable modems, set top boxes, and dsl modems industrial power supplies; general purposesupplies 5v or 12v input dc-dc regulators low-voltage distributed power supplies general description applications features lg vcc 4 3 2 1 ocs boot fb comp/en 5 6 7 8 ug ph 9 gnd psop-8l (UP9305s/w) pin configuration lg vcc 4 3 2 1 gnd boot fb comp/en 5 6 7 8 ug ph 9 gnd psop-8l (UP9305q/t)
upi confidential UP9305 2 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual eman ni pn oitcnufnip toob ylppus partstoob n eewtebroticapacpartstoobehttcennoc.revirdetagreppug nitaolfehtrof e grahcehtsedivorproticapacpartstoobeht.tiucricpartst ooba mrofotniphpehtdnaniptoob .tefsomreppuehtnonrutot gu .tuptuorevirdetagreppu d erotinom sinipsiht.tefsomreppufoetagehtotnipsihttcennoc d enrutsahtefsomreppuehtnehwenimretedotyrtiucricnoitc etorphguorht-toohsevitpadaehtyb .ffo dng .dnuorg sco .gnittesnoitcetorptnerrucrevo .levelpco ehttesotdng otnipsihtmorfrotsiseratcennoc gl .tuptuorevirdetagrewol d erotinom sinipsiht.tefsomrewolfoetagehtotnipsihttcennoc d enrutsahtefsomrewolehtnehwenimretedotyrtiucricnoitc etorphguorht-toohsevitpadaehtyb .ffo ccv .egatlovylppus t cennoc.revirdetagrewolehtdna5039puehtrofylppussaibe htsedivorpnipsiht s iroticapacgnilpuocedatahterusne.nipsihtotegatlovylp pusv2.31otv5.4delpuoced-llew a .ciehtraendecalp bf .egatlovkcabdeef e htmorfredividrotsisera.reifilpmarorreehtottupnignit revniehtsinipsiht ne/pmocehthtiwnoitanibmocninipsihtesu.egatlovnoital ugerehttesotdesusidng ottuptuo .retrevnocehtfopoolkcabdeeflortnocegatlovehtetasnep mocotnip ne/pmoc .tuptuoreifilpmarorre e htfotupnignitrevni-nonehtdnareifilpmarorreehtfotupt uoehtsisiht l ortnoc-egatlovehtetasnepmocotnipbfehthtiwnoitanibmo cninipsihtesu.rotarapmoc m w p d narellortnocehtselbasidv3.0woleblevelaotne/pmocgnil lup.retrevnocehtfopoolkcabdeef .woldlehebotstuptuogldnagueht,potsotrotallicsoehtse suac hp .edon hctiws esahp e htfoniardehtdnatefsomreppuehtfoecruosehtotnipsihttc ennoc s sorcapordegatlovehtrotinom otdna,revirdguehtrofknisehtsadesusinipsiht.tefsomre wol -t oohsevitpadaehtybderotinom oslasinipsiht.noitcetorptnerrucrevoroftefsomrewoleh t .ffodenrutsahtefsomreppuehtnehwenimretedotyrtiucric noitcetorphguorht dapdesopxe .dnuorg e htotderedlosllewebdluohsdnahtapgnitcudnoctaehetanim odehtsidapdesopxeeht .ecnamrofreplamrehtlamitporofsaivelpitlum htiw bcp functional pin description ordering information rebmunredr oe pytegakca pv fer krame rg nikram pot 8uss5039pu l8-posp v6. 0p coraeni lf fo-hctalpv us 5039pu 8ust5039p uv 8. 0v m522@ pco dexi ff fo-hctalpv ut 5039pu 8usq5039p uv 8. 0v m003@ pco dexi ff fo-hctalpv uq 5039pu 8usw5039p uv 6. 0p coraeni l) puccih(ffo-hctalnon pv uw 5039pu note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes.
upi confidential UP9305 3 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual typical application circuit functional block diagram boot ug lg ph fb vcc v in v out comp/en gnd shut down r1r2 ocs 0.3v pwm vcc 1.0v vcc gnd lg ug boot fb comp/en v ocp 4.2v vdd ss error amplifier oscillator ocp gate control logic soft start por internal regulator enable logic pwm comparator por enable protection v fb uvp 0.3xv ref v fb ovp 1.25xv ref ph ocs v ref UP9305s/w 0.6v UP9305t/q 0.8v
upi confidential UP9305 4 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual the UP9305 is a compact synchronous-rectified buck controller specifically designed to operate from 5v or 12v supply voltage and to deliver high quality output voltage as low as 0.6v. supply voltage the vcc pin receives a well-decoupled 4.5v to 13.2v supply voltage to power the control circuit, the lower gate driver and the bootstrap circuit for the higher gate driver. a minimum 1uf ceramic capacitor is recommended to bypass the supply voltage. place the bypassing capacitor physically near the ic. an internal linear regulator regulates the supply voltage into a 4.2v voltage vdd for internal control logic circuit. no external bypass capacitor is required for filtering the vdd voltage. the UP9305 integrates mosfet gate drives that are powered from the vcc pin and support 12v+12v driving capability. a bootstrap diode is embedded to facilitate pcb design and reduce the total bom cost. no external schottky diode is required. converters that consist of UP9305 feature high efficiency without special consideration on the selection of mosfets. note: the embedded bootstrap diode is not a schottky diode having a 0.8v forward voltage. external schottky diode is highly recommended if the vcc voltage is expected to be lower than 5.0v. otherwise the bootstrap diode may be too low for the device to work normally. power on reset and chip enable a power on reset (por) circuitry continuously monitors the supply voltage at vcc pin. once the rising por threshold is exceeded, the UP9305 sets itself to active state and is ready to accept chip enable command. the rising por threshold is typically 4.2v at vcc rising. the comp/en is a multifunctional pin: control loop compensation and chip enable as shown in figure 1. an enable comparator monitors the comp/en pin voltage for chip enable. a signal level transistor is adequate to pull this pin down to ground and shut down the UP9305. an 80ua current source charges the external compensation network with 1.0v ceiling when this pin is released. if the voltage at comp/en pin exceeds 0.3v, the UP9305 initiates its softstart cycle. the 80ua current source keeps charging the comp pin to its ceiling until the feedback loop boosts the comp pin higher than 0.8v according to the feedback signal. the current source is cut off when v comp is higher than 1.0v during normal operation. fb enable disable comp/en v ref 0.3v 1v chip enable error amplifier UP9305 figure 1. chip enable function soft starta built-in soft start is used to prevent surge current from power supply input during turn on (referring to the functional block diagram). the error amplifier is a three-input device. reference voltage v ref or the internal soft start voltage ss whichever is smaller dominates the behavior of the non- inverting inputs of the error amplifier. ss internally ramps up to vcc and the output voltage will follow the ss signal and ramp up smoothly to its target level. the ss signal keeps ramping up after it exceeds the reference voltage v ref . however, the reference voltage v ref takes over the behavior of error amplifier after ss > v ref . when the ss signal climb to 1.3 x v ref , the UP9305 claims the end of softstart cycle and enables the over and under voltage protection of the output voltage. figure 2 shows a typical start up interval for UP9305 where the comp/sd pin has been released from a grounded (system shutdown) state. the internal 80ua current source starts to charge the compensation network after the comp/sd pin is released from grounded at t1. the comp/sd exceeds 0.3v and enables the UP9305 at t2. the comp/sd continues ramping up and stays at 1v before the ss starts ramping up at t3. the UP9305 initializes itself such as current limit level setting (see the relative section) during the time interval between t2 and t3. the output voltage follows the internal ss and ramps up to its final level during t3 and t4. at t4, the reference voltage v ref takes over the behavior of the error amplifier as the internal ss crosses v ref . the internal ss keeps ramping up and reaches 1.3 x v ref at t5, where the UP9305 asserts the end of softstart cycle. functional description
upi confidential UP9305 5 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual t1 t2 t3 t4 t5 ramp comp/en ss v out v ref 0.3v comp (1v/div) lgate (10v/div) v out (1v/div) figure 2. softstart behavior of UP9305. power input detectionthe UP9305 detects ph voltage for the present of power input when the ug turns on the first time. if the ph voltage does not exceed 1.0v when the ug turns on, the UP9305 asserts that power input in not ready and stops the softstart cycle. another softstart cycle is initiate after a 6ms time delay. figure 4 shows the start up interval where v in does not present initially. v in (5v/div) lgate (10v/div) v out (1v/div) i l (5a/div) figure 3. softstart where v in does not present initially. functional description output voltage selection the output voltage can be programmed to any level between the reference voltage v ref up to the 90% of v in supply. the lower limitation of output voltage is caused by the internalreference. the upper limitation of the output voltage is caused by the maximum available duty cycle (90% typical). this is to leave enough time for over current detection. output voltage out of this range is not allowed. an voltage divider sets the output voltage (refer to the typical application circuit on page 3 for detail). in real applications, choose r1 in 1k ~ 10k range and choose appropriate r2 according to the desired output voltage. 2r 2 r 1r v v ref out + = over current protection (ocp) the UP9305 detects voltage drop across the lower mosfet (v phase ) for over current protection when it is turned on. if v phase is lower than the user-programmable voltage v ocp , the UP9305 asserts ocp and shuts down the converter. the ocp level can be programmed by ocs pin (UP9305s/ w) or fixed at 300mv (UP9305q). the UP9305 sources a 20ua current source out of ocs pin. connect resistor r ocs at ocs pin to create voltage level v ocs for ocp setting. the maximum of v ocp should not be larger than 375mv. 4 r ua 20 v ocs ocs = ocs ocp v v = ) on ( ds ocp ocp r v i = (a) for example: if v ocp = 375mv, and r ds(on) = 10m , the i ocp will be 37.5a. if v ocp = 225mv, and r ds(on) = 10m , the i ocp will be 22.5a. over voltage and under voltage protection the UP9305 asserts over voltage protection if the feedback voltage v fb is higher than 125% of reference voltage v ref . the UP9305 asserts under voltage protection if the feedback voltage v fb is lower than 30% of reference voltage v ref after soft start end. the UP9305 turns off both higher and lower gate drivers upon uvp and turns on lower gate driver upon ovp. the latch-off type uvp/ovp protection can be reset by por or toggling the comp/en pin. UP9305w is non latch-off (hiccup) uvp type. pv up vo q/t/s5039p uf fo-hcta lf fo-hctal w5039p u) puccih(ffohctalno nf fo-hctal time 2ms/div time 4ms/div
upi confidential UP9305 6 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual package thermal resistance (note 3) psop-8l ja ----------------------------------------------------------------------------------------------------------------- 47 o c/w psop-8l jc ---------------------------------------------------------------------------------------------------------------- 17.9 o c/w power dissipation, p d @ t a = 25 o c psop-8l ----------------------------------------------------------------------------------------------------------------------------- 2.13w (note 4) operating junction temperature ra nge ------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature ra nge --------------------------------------------------------------------------------- -40 o c to +85 o c supply input voltage, v cc ----------------------------------------------------------------------------------------------------- +4.5v to 13.2v absolute maximum rating thermal information recommended operation conditions (note 1) supply input voltage, vcc -------------------------------------------------------------------------------------- -0.3v to +15v boot to ph --------------------------------------------------------------------------------------------------------------------- -0.3v to +15v ph to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0.7v to 15v < 200ns --------------------------------------------------------------------------------------------------------------------- - 8v to 30v boot to gnd dc --------------------------------------------------------------------------------------------------------------- -0.3v to vcc + 15v < 200ns ------------------------------------------------------------------------------------------------------------------ -0.3 v to 42v ug to ph dc------------------------------------------------------------------------------------------------------- -0.3v to (boot - ph +0.3v) <200ns ------------------------------------------------------------------------------------------------ -5v to (boot - ph + 0. 3v) lg to gnd dc ---------------------------------------------------------------------------------------------------------- -0.3v to + (vcc + 0.3v) <200ns ---------------------------------------------------------------------------------------------------------- -5v to vcc + 0.3v other pins -------------------------------------------------------------------------------------------------------------------- ------ -0.3v to +6v storage temperature range ----------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature --------------------------------------------------------------------------------------------------------------------- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) ------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) --------------------------------------------------------------------------------------------------------------- 200v note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions.
upi confidential UP9305 7 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus egatlovylppu sv cc 5. 4- -2 .3 1v tnerrucylppu si cc v,nepo gldnagu cc ,v21= gnihctiws - -3- -a m tnerrucylppustnecseiu qi q_cc v bf v= fer gnihctiwson,v1.0 +- -3 . 1- -a m egatlovtupnirewo pv ni 0. 3- -2 .3 1v teser norewop dlohserhtro pv htrcc v cc gnisi r0 . 42 . 44 . 4v siseretsyh ro pv syhcc - -5 . 0- -v ycneuqerfgnihctiws ycneuqerfgninnureer ff cso 07 20 0 30 3 3z hk edutilpmapmar ? v cso v cc v21 =- -3- -v p-p egatlovecnerefer ycaruccaegatlovecnereferlanretn iv bf w/s5039p u4 95. 00 6. 06 06. 0v q/t5039p u2 97. 00 08. 08 08. 0v reifilpmarorre niag cdpoolnep oo an gisedybdeetnarau g5 50 7- -b d tcudorphtdiwdnab-nia gw b gn gisedybdeetnarau g- -0 1- -z hm etar wel sr sn gisedybdeetnarau g3 6 - -s u/v ecnatcudnocsnart 00 60 0 80 00 1v /au tnerrucecruostuptu ov bf v< fer 0 80 2 1- -a u tnerrucknistuptu ov bf v> fer 0 80 2 1- -a u egatlovtesffotupni 0.1 -00 . 1v m tnerrucegakaeltupni - -1 . 00 . 1a n srevirdetagrellortnoc m w p ecruosetagrepp ur crs_gu i gu ecruosam001 =- -3- - knisetagrepp ur kns_gu i gu knis am001 =- -5 . 1- - ecruosetagrewo lr crs_gl i gl ecruosam001 =- -3- - knisetagrewo lr kns_gl i gl knis am001 =- -1- - electrical characteristics (v cc = 12v, t a = 25 o c, unless otherwise specified)
upi confidential UP9305 8 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu srevirdetagrellortnoc m w p yaledgnisir glotgnillafh pv hp votv2.1< gl v2.1 >- -0 3- -s n yaledgnisir guotgnillaf g lv gl v(otv2.1< gu v- hp v2.1> )- -0 3- -s n elcycytud muminim - -0- -% elcycytud mumixam 5 80 95 9% tratstfos emittratstfos votdesaelerne/pmoc morf tuo ni noitaluger - -5 . 2- -s m noitcetorp noitcetorpegatlovredn uv pvu_bf vfoegatnecrep fer - -0 3- -% noitcetorpegatlovrev ov pvo_bf vfoegatnecrep fer - -5 2 1- -% yalednoitcetorpegatlovrevo - -0 2- -s u dlohserhttnerrucrev ov hp t5039p u- -5 22 -- - vm q5039p u- -0 03 -- - egnarelbam margorp pc ov pco w/s5039p u5 73 -- -0 01 -v m pcoroftnerrucecruos sco gnittes i sco - -0 2- -a u emityaled pco - -3 3. 3- -s u dlohserhtelbasi dv ne/pmoc 52. 03 . 05 3. 0v noitcetorperutarepmetrevo - -0 5 1- - o c electrical characteristics
upi confidential UP9305 9 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual application information component selection guidelinesthe selection of external component is primarily determined by the maximum load current and begins with the selection of power mosfet switches. the desired amount of ripple current and operating frequency largely determines the inductor value. finally, c in is selected for its capability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. power mosfet selection the UP9305 requires two external n-channel power mosfets for upper (controlled) and lower (synchronous) switches. important parameters for the power mosfets are the breakdown voltage v (br)dss , on-resistance r ds(on) , reverse transfer capacitance c rss , maximum current i ds(max) , gate supply requirements, and thermal management requirements. the gate drive voltage is supplied by vcc pin that receives 4.5v~13.2v supply voltage. when operating with a 7~13.2v power supply for vcc, a wide variety of nmosfets can be used. logic-level threshold mosfet should be used if the input voltage is expected to drop below 7v. caution should be exercised with devices exhibiting very low v gs(on) characteristics. the shoot-through protection present aboard the UP9305 may be circumvented by these mosfets if they have large parasitic impedances and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 30ns or so. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components: conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty cycle. since the UP9305 is operating in continuous conduction mode, the duty cycles for the mosfets are: in out up v v d = ; in out in low v v v d ? = the resulting power dissipation in the mosfets at maximum output current are: osc sw in out up ) on ( ds 2 out up f t v i 5.0 d r i p + = low ) on ( ds 2out low d r i p = where t sw is the combined switch on and off time. both mosfets have i 2 r losses and the upper mosfet includes an additional term for switching losses, which are largest at high input voltages. the lower mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. these equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the lower mosfets body diode. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the gate-charge losses are mainly dissipated by the UP9305 and dont heat the mosfets. however, large gate charge increases the switching interval, t sw that increases the mosfet switching losses. the gate-charge losses are calculated as: os c up _ rss in lo _ iss up _ iss cc cc c_g f) c v ) c c( v( v p + + = where c iss_up is the input capacitance of the upper mosfet, c iss_low is the input capacitance of the lower mosfet, and c rss_up is the reverse transfer capacitance of the upper mosfet. make sure that the gate-charge loss will not cause over temperature at UP9305, especially with large gate capacitance and high supply voltage. output inductor selection output inductor selection usually is based on the considerations of inductance, rated current, size requirements and dc resistance (dcr). given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ) v v 1( v l f 1 i in out out out osc l ? = ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 20% of i out(max) . there is another tradeoff between output ripple current/ voltage and response time to a transient load. increasing the value of inductance reduces the output ripple current and voltage. however, the large inductance values reduce the converters response time to a load transient.
upi confidential UP9305 10 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual application information maximum current ratings of the inductor are generally specified in two methods: permissible dc current and saturation current. permissible dc current is the allowable dc current that causes 40 o c temperature raise. the saturation current is the allowable current that causes 10% inductance loss. make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. the size requirements refer to the area and height requirement for a particular design. for better efficiency, choose a low dc resistance inductor. dcr is usually inversely proportional to size. input capacitor selection the synchronous-rectified buck converter draws pulsed current with sharp edges from the input capacitor, resulting in ripples and spikes at the input supply voltage. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper mosfet turns on. place the small ceramic capacitors physically close to the mosfets to avoid the stray inductance along the connection trace. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck converter is calculated as: in out in out ) max ( out ) rms ( in v ) v v( v i i ? = this formula has a maximum at v in = 2v out , where i in(rems) = i out(rms) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. always consult the manufacturer if there is any question. for a through-hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. output capacitor selection the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the equivalent ripple current into the output capacitor is half of the inductor ripple current while the equivalent frequency is double of phase operation frequency due to two phase operation the output ripple ? v out is approximately bounded by: ) c f 16 1 esr ( 2 i v out osc l out + ? = ? since ? i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitors esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capa citors esr value is related to the case size with lower esr available in larger case sizes. bootstrap capacitor selection an external bootstrap capacitor c boot connected to the boot pin supplies the gate drive voltage for the upper mosfet. this capacitor is charged through the internal
upi confidential UP9305 11 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual application information diode when the ph node is low. when the upper mosfet turns on, the ph node rises to v in and the boot pin rises to approximately v in + v cc . the boot capacitor needs to store about 100 times the gate charge required by the upper mosfet. in most applications 0.47 f to 1 f, x 5 r or x7r dielectric capacitor is adequate. feedback loop compensation figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter consisting of UP9305. the control loop includes a compensator and a modulator, where the modulator consists of the pwm comparator, the power stage amplifier and the output filter; the compensator consists of the error amplifier and compensating network. a well-designed feedback loop tightly regulates the output voltage (v out ) to the reference voltage v ref with fast response to load/line transient and good stability. the goal of the compensation network is to provide and the highest 0db crossing frequency and adequate phase margin (greater than 45 degrees). it is also recommended to manipulate loop frequency response that its gain crosses over 0db at a slope of - 20db/dec. v in v out l out c out esr ph r1 c1 c2 r2 r3 c3 error amp. pwm comp. driver v osc v ref v comp z fb z comp modulator compensator figure 5. voltage control loop using UP9305. modulator break frequency equations the error amplifier output (v comp ) is compared with the oscillator (osc) sawtooth waveform to provide a pulse- width modulated (pwm) waveform with an amplitude of v in at the ph node. the pwm waveform is smoothed by the output filter (l out and c out ). the modulator transfer function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain and the output filter (l out and c out ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage g v osc . the output lc filter introduces a double pole, 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. the resonant frequency of the lc filter expressed as: out out lc c l 2 1 f = the esr zero is contributed by the esr associated with the output capacitor. note that this requires that the output capacitor should have enough esr to satisfy stability requirements as described in the later sections. the esr zero of the output capacitor expressed as: ou t esr c esr 2 1 f = figure 6 illustrates frequency response of a typical modulator using UP9305. -60 -40 -20 0 20 40 60 80 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) gain (db) lc double pole esr zero figure 6. frequency response of modulator. 2) compensator frequency equations the UP9305 adopts an operational transconductance amplifier (ota) as the error amplifier as shown in figure 7. ea+ ea- r out gm ? v m ? i out = gm x ? v m v ou t figure 7. operational transconductance amplifier.
upi confidential UP9305 12 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual application information the transconductance is defined as: m out v i g m ? ? = where ? v m = (ea+) - (ea-); ? i out = e/a output current. figure 8 illustrates a type ii compensation network using ota. the compensation network consists of the error amplifier and the impedance networks z fb and z comp . v ref c2 c1 r1 r2 r3 v out v comp error amplifier gm z comp z fb figure 8. type ii compensation network using ota. the compensator transfer function is the small-signal transfer function of v comp /v out . this function is dominated by a mid-band gain and compensation network z comp , with a pole at f p1 and a zero at f z1 . the mid-band gain of the compensation is expressed as: g m 1r 3r 2r 2r gain _ band _ m id = the equations below relate the compensation networks pole and zero to the components (r1, c1, and c2) in figure 9. ) 2c 1c 2c 1c (1r 2 1 f 1p + = ; 1 c 1r 2 1 f 1z = -60 -40 -20 0 20 40 60 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) gain (db) c1 r1 loop gain compensator gain modulator gain f p1 f z1 figure 9. frequency response of type ii compensation. figure 10 shows the dc-dc converters gain vs. frequency. careful design of z comp and z fb provides tight regulation and fast response to load/line transient with good stability. follow the guidelines for locating the poles and zeros of the compensation network. 1. pick mid-band gain (r1) for desired converter band- width. 2. place zero (c1) below lc double pole (~25% f lc ). 3. place pole (c2) at half the switching frequency. 4. check gain against error amplifier open loop gain. 5. estimate phase margin - repeat if necessary. -60 -40 -20 0 20 40 60 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) gain (db) loop gain compensator gain modulator gain figure 10. frequency response of type ii compensation. design example as a design example, take a power supply with the following specifications: v in = 10.8v to 13.2v (12v nominal), v out = 1.2v ? 5%, i out(max) = 20a, f osc = 300khz/200khz, ? v out = 20mv, bandwidth = 50khz. 1.) power component selection first, choose the inductor for about 20% ripple current at the maximum v in : ) v v 1( v l f 1 i in out out out osc l ? = ? ) v2. 13 v2.1 1( v2.1 l khz 300 1 % 20 a 20 i out l ? = = ? uh 9.0 l out = selecting a standard value of 1.0uh results in a maximum ripple current of 3.6a. choose two 1000uf capacitors with 10m esr in parallel to yield equivalent esr = 5m . the output ripple voltage is about 18mv accordingly. an optional 22uf ceramic output capacitor is recommended to minimize the effect of esl in the output ripple.
upi confidential UP9305 13 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual application information the modulator dc gain and break frequencies are calculated as: d b 5. 16 ) 8.1 12 log( 20 ) v v log( 20 gain d c osc in = = ? = kh z 56 .3 10 2000 10 1 2 1 f 6 6 lc = = ? ? kh z 16 10 2000 10 5 2 1 f 6 3 esr = = ? ? 2.) compensation select r2 = 10k and r3 = 5k to set output voltage as 1.2v. r2 and r3 do not affect the compensation, 1k ~ 10k is adequate for the application. the modulator gain at zero-crossing frequency (50khz) is calculated as -19.5db. this demands a compensator with mid-band gain as 19.5db. select r1 as: = = k7. 17 v gm v 10 1 r ref out ) 20 /5. 19 ( select c1 = 10nf to place f z1 = 0.9khz, about one forth of the lc double pole. select c2 = 68pf to place f p1 = 133khz, about half of the switching frequency. figure 11 shows the result loop gain vs. frequency relation. -60 -40 -20 0 20 40 60 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) gain (db) loop gain compensator gain modulator gain figure 11. gain vs. frequency for the design example. type iii compensation the esr zero plays an important role in type ii compensation. output capacitors with low esr and small capacitance push the esr zero to high frequency band. if the esr zero is ten times higher than the lc double pole, the double pole may cause the loop phase close to 180 o and make the control loop unstable. a type ii compensation cannot stabilize the loop since it has only one zero. a type iii compensation network as shown in figure 12 that features 2 poles and 2 zeros is necessary for such applications where esr zero is far away from the lc double pole. adding a feedforward capacitor c3 on original type ii compensation network introduces an additional pole-zero pair ( z2 and p2) as illustrated in figure 13. the new pole- zero pair are expressed as: 3 c 3r 2 1 2z = ; ) 3r 2r /( )3r 2r( 3c 2 1 2 p + = v ref c2 c1 r1 r2 r3 c3 v out v comp error amplifier gm z comp z fb figure 12. type iii compensation network. while the mid-band gain remains unchanged, theadditional pole-zero pair causes a gain boost at the flat gain region. the gain-boost is limited by the ratio (r1 +r2)/ r2. figures 14 shows the dc-dc converters gain vs. frequency. -60 -40 -20 0 20 40 60 80 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) gain (db) loop gain compensator gain modulator gain p1 p2 z1 z2 figure 13. loop gain of type iii compensation network.
upi confidential UP9305 14 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual application information -60 -40 -20 0 20 40 60 80 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) gain (db) loop gain compensator gain modulator gain figure 14. frequency response of type iii compensa- tion. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ? i load x(esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. pcb layout considerations high speed switching and relatively large peak currents in a synchronous-rectified buck converter make the pcb layout a very important part of design. fast current switching from one device to another in a synchronous- rectified buck converter causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. careful component placement layout and printed circuit board design minimizes the voltage spikes induced in the converter. follow the layout guidelines for optimal performance of UP9305. 1 the upper and lower mosfets turn on/off and conduct pulsed current alternatively with high slew rate transition. any inductance in the switched current path generates a large voltage spike during the switching. the interconnecting wires indicated by red heavy lines conduct pulsed current with sharp transient and should be part of a ground or power plane in a printed circuit board to minimize the voltage spike. make all the connection the top layer with wide, copper filled areas. 2 place the power components as physically close as possible. 2.1 place the input capacitors, especially the high frequency ceramic decoupling capacitors, directly to the drain of upper mosfet ad the source of the lower mosfet. to reduce the esr replace the single input capacitor with two parallel units 2.2 place the output capacitor between the converter and load. 3 place the UP9305 near the upper and lower mosfets with ug and lg facing the power components. keep the components connected to noise sensitive pins near the UP9305 and away from the inductor and other noise sources. 4 use a dedicated grounding plane and use vias to ground all critical components to this layer. the ground plane layer should not have any traces and should be as close as possible to the layer with power mosfets. use an immediate via to connect the components to ground plane including gnd of UP9305. use several bigger vias for power components. 5 apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes to maintain good voltage filtering and to keep power losses low. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. 6 the ph node is subject to very high dv/dt voltages. stray capacitance between this island and the surrounding circuitry tend to induce current spike and capacitive noise coupling. keep the sensitive circuit away from the ph node and keep the pcb area small to limit the capacitive coupling. however, the pcb area should be kept moderate since it also acts as main heat convection path of the lower mosfet. 7 the UP9305 sources/sinks impulse current with 2a peak to turn on/off the upper and lower mosfets. the connecting trance between the controller and gate/ source of the mosfet should be wide and short to minimize the parasitic inductance along the traces. 8 flood all unused areas on all layers with copper. flooding with copper will reduce the temperature riseof power component. 9 provide local vcc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as possible to the boot and ph pins.
upi confidential UP9305 15 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual package information psop - 8l note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. 0.31 - 0.51 4.80 - 5.00 5.79 - 6.20 0.10 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 1.80 - 2.40 1.80 - 2.40 0.00 - 0.15 1.7 max 1
upi confidential UP9305 16 UP9305-ds-c3000, aug. 2015 www.upi-semi.com conceptual important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2015, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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